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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. april 2010 doc id 17196 rev 1 1/11 11 STL23N85K5 n-channel 850 v, 0.23 ? , 18 a powerflat? 8x8 hv zener-protected supermesh 5? power mosfet features powerflat? 8x8 hv worldwide best r ds(on) worldwide best fom (figure of merit) ultra low gate charge 100% avalanche tested zener-protected application switching applications description supermesh 5? is a revolutionary avalanche- rugged very high voltage power mosfet technology based on an innovative proprietary vertical structure. the result is a drastic reduction in on-resistance and ultra low gate charge for applications which require superior power density and high efficiency. figure 1. internal schematic diagram type v dss r ds(on) max i d p w STL23N85K5 850 v < 0.275 ? 18 (1) 1. the value is rated according to r thj-c . 210 3 3 3 ' $ 0ower&,!4?x(6 d(2) g(1) s(3) am01476v1 table 1. device summary order code marking package packaging STL23N85K5 23n85k5 powerflat? 8x8 hv tube www.st.com
contents STL23N85K5 2/11 doc id 17196 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STL23N85K5 electrical ratings doc id 17196 rev 1 3/11 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v gs gate-source voltage 30 v i d (1) 1. the value is rated according to r thj-case. drain current (continuous) at t c = 25 c 18 a i d (1) drain current (continuous) at t c = 100 c 11 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 72 a i d (3) 3. when mounted on fr-4 board of inch2, 2oz cu. drain current (continuous) at t c = 25 c 2.1 a i d (3) drain current (continuous) at t c = 100 c 1.35 a i dm (2),(3) drain current (pulsed) 8.4 a p tot (1) total dissipation at t c = 25 c (steady state) 210 w p tot (3) total dissipation at t c = 25 c (steady state) 3 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) tbd a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) tbd mj dv/dt (4) 4. i sd tbd a, di/dt 100 a/s, v peak < v (br)dss. peak diode recovery voltage slope tbd v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature 150 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max (drain) 0.6 c/w r thj-amb (1) 1. when mounted on fr-4 board of inch2, 2oz cu. thermal resistance junction-amb max 45 c/w t l maximum lead temperature for soldering purpose 300 c
electrical characteristics STL23N85K5 4/11 doc id 17196 rev 1 2 electrical characteristics (t case = 25 c unless otherwise specified). table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1 ma, v gs = 0 850 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating, v ds = max rating,tc=125 c 1 50 a a i gss gate body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 8.5 a 0.230 0.275 ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds =100 v, f=1 mhz, v gs =0 - 1650 - pf c oss output capacitance 115 pf c rss reverse transfer capacitance 2pf c o(tr) (1) 1. time related is defined as a c onstant equivalent capacitance givi ng the same charging time as c oss when v ds increases from 0 to 80% v dss. equivalent capacitance time related v gs = 0, v ds = 0 to 680 v -tbd- pf c o(er) (2) 2. energy related is defined as a constant equivalent capacitance gi ving the same stored energy as c oss when v ds increases from 0 to 80% v dss. equivalent capacitance energy related -tbd- pf r g intrinsic gate resistance f = 1 mhz open drain - 3.5 - ? q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 680 v, i d = 8.5 a v gs =10 v (see figure 3 ) - 35 tbd tbd - nc nc nc
STL23N85K5 electrical characteristics doc id 17196 rev 1 5/11 the built-in-back zener diodes have specific ally been designed to enhance not only the device?s esd capability, but also to make them safely absorb possible vo ltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device?s integrity. these integrated zener diodes thus avoid the usage of external components. table 6. switching times symbol parameter test cond itions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 400 v, i d = 8.5 a, r g =4.7 ? , v gs =10 v (see figure 5 ) - tbd tbd tbd tbd - ns ns ns ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm source-drain current source-drain current (pulsed) - tbd tbd a a v sd (1) 1. pulsed: pulse duration = 300s, duty cycle 1.5%. forward on voltage i sd = 8.5 a, v gs =0 - 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 17 a, v dd = 60 v di/dt = 100 a/s, (see figure 4 ) - tbd tbd tbd ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 17 a,v dd = 60 v di/dt=100 a/s, t j =150 c (see figure 4 ) - tbd tbd tbd ns c a table 8. gate-source zener diode symbol parameter test conditions min typ. max unit bv gso gate-source breakdown voltage igs 1ma, (open drain) 30 - - v
test circuits STL23N85K5 6/11 doc id 17196 rev 1 3 test circuits figure 2. switching times test circuit for resistive load figure 3. gate charge test circuit figure 4. test circuit for inductive load switching and diode recovery times figure 5. unclamped inductive load test circuit figure 6. unclamped inductive wavefor m figure 7. switching time waveform am0146 8 v1 v g s p w v d r g r l d.u.t. 2200 f 3 . 3 f v dd am01469v1 v dd 47k ? 1k ? 47k ? 2.7k ? 1k ? 12v v i =20v=v gmax 2200 f p w i g =con s t 100 ? 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 ? a a b b r g g fa s t diode d s l=100 h f 3 . 3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3 . 3 f v dd am01472v1 v (br)d ss v dd v dd v d i dm i d am0147 3 v1 v d s t on td on td off t off t f t r 90 % 10 % 10 % 0 0 90 % 90 % 10 % v g s
STL23N85K5 package mechanical data doc id 17196 rev 1 7/11 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark.
package mechanical data STL23N85K5 8/11 doc id 17196 rev 1 table 9. powerflat? 8x8 hv mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 b 0.95 1.00 1.05 c0.10 d8.00 e8.00 d2 7.05 7.20 7.30 e2 4.15 4.30 4.40 e2.00 l 0.40 0.50 0.60 figure 8. powerflat? 8x8 hv drawing mechanical data index area top view plane seating 0.08 c bottom view side view pin#1 id d e e b a e2 d2 l 0.40 a1 am05542v1
STL23N85K5 package mechanical data doc id 17196 rev 1 9/11 figure 9. powerflat? 8x8 hv recommended footprint 7. 3 0 4.40 2.00 0.60 1.05 am0554 3 v1
revision history STL23N85K5 10/11 doc id 17196 rev 1 5 revision history table 10. document revision history date revision changes 26-apr-2010 1 first release.
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